Latches, Flip-Flop and Pewaktu (Timer)

Juni 09, 2021

Latches, Flip-Flop and Pewaktu (Timer)

Latches, Flip-Flop and Pewaktu (Timer)

Latches

Definition :

The output of a latch depends on its current inputs and on its previous output and its change of state can happen at any time when its inputs change.

· S-R (Set-Reset) Latch

· Gated S-R Latch

· Gated D Latch

S-R Latch

Active-LOW Input /S-/R Latch

The Gated S-R Latch

A gated latch requires an Enable input, EN (G is also used to designated an enable input). The S and R inputs control the state to which the latch will go when a HIGH level is applied to the EN input. The latch will not change until EN is HIGH.

Truth Table for Gated S-R Latch

The Gated D Latch

Only has one input in addition to EN. This input is called the D (data) input. -When the D input is HIGH and the EN input is HIGH, the latch will SET. -When the D input is LOW and EN is HIGH, the latch will RESET. -Another way, the output Q follows the input D when EN is HIGH.

Edge-Triggered Flip-Flops

· Edge-triggered S-R flip-flop

· Edge-triggered D flip-flop

· Edge-triggered J-K flip-flop

The Edge-Triggered S-R Flip-Flop

The S and R inputs of the S-R flip-flop are called synchronous input because data on these inputs are transferred to the flip-flop’s output only on the triggering edge of the clock pulse.

The Edge-Triggered D

FlipFlop The D flip-flop is useful when a single data bit (1 or 0) is to be stored.

The Edge-Triggered J-K Flip-Flop

The J-K flip-flop is versatile and is widely used type of flip-flop. The difference is that he J-K flip-flop has no invalid state as does the S-R flip-flop.